Three-dimensional stacked integrated circuits (3DICs) have been developed to meet multi-functional, low cost, high density, high powered small and lightweight requirements of electronic products. A 3DIC is an IC chip having multi-layered structures.
Meanwhile, complementary metal oxide semiconductor (CMOS) chips usually have a signal level device structure because performance thereof may suffer from high temperature processes. Also, when critical dimensions of a CMOS device are reduced, signal delay problems thereof increase. Additionally, when the length of wiring between a CMOS device and a CMOS chip increase, energy consumption problems thereof increase. Accordingly, 3DIC technology has been developed to alleviate problems associated with CMOS technology.
Because the length of wiring between an IC device and a IC chip is of a 3DIC chip reduced when compared to a signal level CMOS chip, problems associated with CMOS technology such as increased signal delay, noise and energy consumption are reduced. Also, for 3DIC chips, when compared to signal level CMOS chips high frequency performance is improved when bandwidth increases. Additionally, for 3DIC technology, high density may be achieved without substantially reducing planar size. That is, fabrication of 3DIC chips may be decreased without requiring new semiconductor device technology or equipment.
Despite the above, for nanoscale semiconductor processes, fabrication yields of 3DIC chips are less than desired due to bonding problems and low yields during a through silicon via (TSV) process. A conventional TSV process includes forming through vias in a chip. Next, copper is plated to fill the through vias, thereby forming copper TSVs. In the conventional TSV process, however, copper can not be uniformly plated in the through vias. Thus, non-uniformly filled TSVs result in signal loss and reliability problems. Additionally, when a micro-bumping process is used to stack IC chips, a high solder-reflowing temperature of up to 260° C., results in thermal stress of the chips, thereby reducing product reliability.